The present invention relates to an active matrix liquid crystal display device comprising a row and column array of liquid crystal display elements, each display element having an associated switching device, sets of row and column address conductors connected to the display elements via which selection signals and data signals respectively are applied to the display elements, a row drive circuit for applying selection signals to the row address conductors in respective row address periods and a column drive circuit for applying data signals to the set of column address conductors, which column drive circuit is operable to apply the data signals for the display elements of a row to groups of column address conductors in sequence in respective group address periods, each group comprising a plurality of column address conductors, with the column address conductors in a group being charged in the respective group address period according to the level of their relevant data signals.
Active matrix liquid crystal (LC) display devices suitable for displaying datagraphic or video information are well known. Typical examples of such, which use TFTs (thin film transistors) as the switching devices that are connected between the display element electrodes and the sets of row and column address conductors, and the general manner in which they operate, are described in U.S. Pat. No. 5,130,829. In these devices, a row drive circuit connected to the set of row address conductors scans the row conductors by applying a selection (gating) signal to each row conductor in sequence to turn on the TFTs of a row of display elements, and a column drive circuit connected to the set of column conductors applies data signals to the column conductors in synchronism with scanning of the row conductors by the row drive circuit whereby the display elements of a selected row are charged via their respective TFTs to a level dependent on the value of the data signal on their associated column conductors to produce a required display output. The rows are driven individually in turn during respective row address periods in this manner so as to build up a display picture over one field period, and the array of display elements is repeatedly addressed in similar manner in successive field periods.
For convenience of manufacture and compactness, the row and/or column drive circuits in some display devices, and especially those using polysilicon TFTs, have been integrated on the substrate carrying the TFTs peripherally of the display element array using the same large area electronics technology as that employed for the active matrix circuitry of the array with the circuitry of the drive circuits being fabricated simultaneously and similarly comprising TFTs, conductor lines, etc. Due to limitations in operational performance of the TFTs and the kinds of circuit possible when using TFTs, the column drive circuit is customarily provided in the form of a simple multiplexing circuit, examples of which are described in U.S. Pat. No. 4,890,101, and the paper entitled xe2x80x9cA 1.8-in Poly-Si TFT-LCD for HDTV Projectors with a 5-V Fully Integrated Driverxe2x80x9d by S. Higashi et al in SID 95 Digest, pages 81 to 84. The operation of the column drive circuit is based on a multiplexing technique in which analogue video information (data) is sequentially transferred via multiplexing switches from a plurality of video input lines, to which video information is applied simultaneously, to corresponding groups or blocks of column address conductors with each column conductor in a group being connected via a multiplexer switch to a different video input line. Each column address conductor is connected to a respective output of the circuit and typically in these circuits the operation is such that an output associated with one column conductor becomes high impedance prior to, or while, the data signal for an adjacent column conductor is applied. During a row address (video line) period the multiplexer circuit operates to charge each group of column conductors in turn until all the column conductors in the display device have been charged to a level corresponding to the associated level of the video information on the input lines. Once a group of column conductors has been charged the associated multiplexing switches open and the column conductors become high impedance nodes with the voltage applied being maintained on the column conductor capacitance, and then the next group is charged. The circuit operates in this manner so as to charge all the groups in sequence and to drive each row of display elements in turn in this way during respective row address periods.
It has been found that problems can occur in the display output from the display element array when using such a column drive circuit. Particularly, certain columns in the array may show errors by virtue of the display elements in these columns having incorrect drive levels which results, for example, in a lack of display uniformity when displaying uniform grey fields that manifests itself as highly visible vertical lines in the displayed image. The problem is particularly apparent in high aperture type display devices, for example of the kind described in U.S. Pat. No. 5,641,974 and EP-A-0617310, in which portions of the display element electrodes are arranged to overlap partially the two adjacent column address conductors (and row address conductors) so as to increase their effective apertures.
It is an object of the present invention to provide an active matrix display device of the kind using column drive circuit which operates in the manner of a multiplexing circuit in which the problem of the aforementioned undesirable display output artefacts is overcome or reduced at least to some extent.
According to the present invention there is provided an active matrix liquid crystal display device of the kind described in the opening paragraph which is characterised in that the column drive circuit is arranged to charge in a row address period at least the last column conductor of a group in at least two separate charging periods with the second charging period for the at least last column conductor occurring after the charging period of the next group in the sequence. The extent of the unwanted display artefacts is considerably reduced by multiple charging of the column conductors in this way.
It has been determined that capacitive couplings can occur between adjacent column address conductors, either directly or indirectly, and the presence of such indirect or direct capacitance means that as the voltage on the first column conductor of one group is changed in operation of the column drive circuit, this change in voltage can be coupled onto at least the last column conductor of the previously addressed group (that is, the column conductor adjacent the next addressed group) through such capacitance, thereby disturbing the voltage set on that last column conductor. This results in errors occurring in the voltage on the last column conductor of each group (apart from the last) which errors lead to the aforementioned visible vertical lines in the displayed image. By using more than one charging period for the columns affected, the size of the voltage error occurring on the last column conductor of a group is reduced.
Preferably, the column drive circuit is arranged to charge each column address conductor in at least two separate charging periods with the second charging period for the group occurring after the first charging period of the next group in the sequence. The voltage error caused to the last column conductor of one group as a result of addressing the next group is the most significant. However, voltage errors will also result in other column conductors in the preceding group, although the extent of such errors progressively decreases. While it may be adequate in some cases to arrange for only the last one or two column conductors in a group to be multiply charged, it would be advantageous to arrange for all column conductors to be multiply charged so as to minimise any errors occurring on other column conductors with all columns then being addressed in a similar manner. This may also be convenient when designing the necessary column drive circuitry.
A column conductor need not be fully charged to the level of the video line voltage, i.e. the data signal level, in each charging period and may be only partially charged in the first charge period. Preferably, however, the column conductor is charged at least close to the required level in the first charge period.
In a preferred embodiment, the charging periods for two successive groups are interleaved in time. Thus, for example, in the case of there being two charging periods for each group, the second charging period for a first group occurs after the first charging period for the second group and before the second charging period for that second group, the first and second charging periods for the third group occur respectively before and after the second charging period for the second group, and so on. Alternatively, the column drive circuit could be arranged to order the charging periods differently. For example, all groups may be addressed in succession, constituting one charging period each, and then the operation repeated to provide the second charging periods, still within the same row address period, so that all groups and column conductors again have two charging periods but this time the first charging periods all occur before the second charging periods. This approach would require the use of a linestore.